? semiconductor components industries, llc, 2014 july, 2014 ? rev. 9 1 publication order number: ntd4302/d ntd4302 power mosfet 68 a, 30 v, n?channel dpak/ipak features ? ultra low r ds(on) ? higher efficiency extending battery life ? logic level gate drive ? diode exhibits high speed, soft recovery ? avalanche energy specified ? i dss specified at elevated temperature ? dpak mounting information provided ? these devices are pb?free and are rohs compliant applications ? dc?dc converters ? low voltage motor control ? power management in portable and battery powered products: i.e., computers, printers, cellular and cordless telephones, and pcmcia cards maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain?to?source v oltage v dss 30 vdc gate?to?source voltage ? continuous v gs 20 vdc thermal resistance ? junction?to?case total power dissipation @ t c = 25 c continuous drain current @ t c = 25 c (note 4) continuous drain current @ t c = 100 c r jc p d i d i d 1.65 75 68 43 c/w w a a thermal resistance ? junction?to?ambient (note 2) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c continuous drain current @ t a = 100 c pulsed drain current (note 3) r ja p d i d i d i dm 67 1.87 11.3 7.1 36 c/w w a a a thermal resistance ? junction?to?ambient (note 1) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c continuous drain current @ t a = 100 c pulsed drain current (note 3) r ja p d i d i d i dm 120 1.04 8.4 5.3 28 c/w w a a a operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 30 vdc, v gs = 10 vdc, peak i l = 17 apk, l = 5.0 mh, r g = 25 ) e as 722 mj maximum lead temperature for soldering purposes, 1/8 in from case for 10 seconds t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. when surface mounted to an fr4 board using the minimum recommended pad size. 2. when surface mounted to an fr4 board using 0.5 sq. in. drain pad size. 3. pulse test: pulse width = 300 s, duty cycle = 2%. 4. current limited by internal lead wires. http://onsemi.com marking diagrams & pin assignments a = assembly location* y = year ww = work week t4302 = device code g = pb?free package 1 gate 3 source 2 drain 4 drain dpak case 369c (surface mount) style 2 ayww t 4302g 1 2 3 4 1 gate 3 source 2 drain 4 drain ipak case 369d (straight lead) style 2 1 2 3 4 n?channel d s g 30 v 7.8 m @ 10 v r ds(on) typ 68 a i d max v (br)dss see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information ayww t 4302g * the assembly location code (a) is front side optional. in cases where the assembly location is stamped in the package, the front side assembly code may be blank.
ntd4302 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?source breakdown voltage (v gs = 0 vdc, i d = 250 a) positive temperature coefficient v (br)dss 30 ? ? 25 ? ? vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = 30 vdc, t j = 25 c) (v gs = 0 vdc, v ds = 30 vdc, t j = 125 c) i dss ? ? ? ? 1.0 10 adc gate?body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics gate threshold voltage (v ds = v gs , i d = 250 adc) negative temperature coefficient v gs(th) 1.0 ? 1.9 ?3.8 3.0 ? vdc static drain?source on?state resistance (v gs = 10 vdc, i d = 20 adc) (v gs = 10 vdc, i d = 10 adc) (v gs = 4.5 vdc, i d = 5.0 adc) r ds(on) ? ? ? 0.0078 0.0078 0.010 0.010 0.010 0.013 forward transconductance (v ds = 15 vdc, i d = 10 adc) gfs ? 20 ? mhos dynamic characteristics input capacitance (v ds = 24 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 2050 2400 pf output capacitance c oss ? 640 800 reverse transfer capacitance c rss ? 225 310 switching characteristics (note 6) turn?on delay time (v dd = 25 vdc, i d = 1.0 adc, v gs = 10 vdc, r g = 6.0 ) t d(on) ? 11 20 ns rise time t r ? 15 25 turn?off delay time t d(off) ? 85 130 fall time t f ? 55 90 turn?on delay time (v dd = 25 vdc, i d = 1.0 adc, v gs = 10 vdc, r g = 2.5 ) t d(on) ? 11 20 ns rise time t r ? 13 20 turn?off delay time t d(off) ? 55 90 fall time t f ? 40 75 turn?on delay time (v dd = 24 vdc, i d = 20 adc, v gs = 10 vdc, r g = 2.5 ) t d(on) ? 15 ? ns rise time t r ? 25 ? turn?off delay time t d(off) ? 40 ? fall time t f ? 58 ? gate charge (v ds = 24 vdc, i d = 2.0 adc, v gs = 10 vdc) q t ? 55 80 nc q gs (q1) ? 5.5 ? q gd (q2) ? 15 ? body?drain diode ratings (note 5) diode forward on?voltage (i s = 2.3 adc, v gs = 0 vdc) (i s = 20 adc, v gs = 0 vdc) (i s = 2.3 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? ? 0.75 0.90 0.65 1.0 ? ? vdc reverse recovery time (i s = 2.3 adc, v gs = 0 vdc, di s /dt = 100 a/ s) t rr ? 39 65 ns t a ? 20 ? t b ? 19 ? reverse recovery stored charge q rr ? 0.043 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. indicates pulse test: pulse width = 300 sec max, duty cycle 2%. 6. switching characteristics are independent of operating junction temperature.
ntd4302 http://onsemi.com 3 typical characteristics 1.6 1.4 1 1.2 0.8 0.6 10 1 100 1000 10000 40 20 50 10 30 0 60 0.005 0 30 2 1.5 1 i d , drain current (amps) 0 v gs , gate?to?source voltage (v) figure 1. on?region characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.1 0.075 0.05 0.025 4 0 26810 figure 3. on?resistance vs. gate?to?source voltage v gs , gate?to?source voltage (v) figure 4. on?resistance vs. drain current and gate voltage i d , drain current (amps) r ds(on) , drain?to?source resistance ( ) figure 5. on?resistance variation with temperature t j , junction temperature ( c) figure 6. drain?to?source leakage current vs. voltage v ds , drain?to?source voltage (v) i dss , leakage (na) 50 ?50 100 75 0 ?25 125 150 23 6 0.00e+00 1.00e+01 0 0.01 0.015 525 20 15 10 3 0 v ds , drain?to?source voltage (v) 10 20 40 2.5 3 v gs = 0 v t j = 150 c t j = 100 c i d = 18.5 a v gs = 10 v v gs = 4.5 v v gs = 10 v t j = 25 c i d = 10 a t j = 25 c v ds > = 10 v t j = 25 c t j = ?55 c t j = 100 c v gs = 10 v v gs = 7 v v gs = 5 v v gs = 4.6 v v gs = 4 v r ds(on) , drain?to?source resistance ( ) r ds(on) , drain?to?source resistance (normalized) v gs = 4.4 v v gs = 3.8 v v gs = 3.4 v v gs = 3.2 v v gs = 3.0 v t j = 25 c 50 25 45 v gs = 2.8 v 0.5 2.00e+01 3.00e+01 4.00e+01 5.00e+01 6.00e+0 1
ntd4302 http://onsemi.com 4 typical characteristics v gs v ds 5 10 7.5 0 12.5 10 10 4000 20 10 0 c, capacitance (pf) 0 q g , total gate charge (nc) figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage vs. total charge v gs , gate?to?source? voltage (v) 1 1000 100 10 10 100 figure 9. resistive switching time variation vs. gate resistance r g , gate resistance ( ) figure 10. diode forward voltage vs. current v sd , source?to?drain voltage (v) i s , source current (amps) t, time (ns) 6000 010 60 0.5 0.9 0.8 0.7 0.6 1 15 5 0 20 25 gate?to?source or drain?to?source voltage (v) 2000 3000 5000 30 2.5 i d = 2 a t j = 25 c q 2 q 1 v gs q t v dd = 24 v i d = 18.5 a v gs = 10 v t r t d(off) t d(on) t f v gs = 0 v t j = 25 c v gs = 0 v v ds = 0 v t j = 25 c c rss c iss c oss c rss c iss 20 30 40 50 1000 v d 15 25 20 0 30 10 v ds , drain?to?source? voltage (v)
ntd4302 http://onsemi.com 5 typical characteristics figure 11. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 dc 1 100 100 10 10 ms 1 ms 100 s v gs = 10 v single pulse t c = 25 c di/dt t rr t a t p i s 0.25 i s time i s t b figure 12. diode reverse recovery waveform r ja (t) = r(t) r ja d curves apply for power pulse train shown read time at t 1 t j(pk) - t a = p (pk) r ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 13. thermal response ? various duty cycles t, time (seconds) rthj a (t) , effective transient thermal resistance 1000 1 d = 0.5 1e-05 1e-03 1e-02 1e-01 0.2 0.01 0.01 0.02 0.05 0.1 1e+00 1e+01 1e+03 single pulse 1e-04 1e+02 mounted to minimum recommended footprint duty cycle 100 10 0.1 ordering information device package type package shipping ? ntd4302g dpak 369c (pb?free) 75 units / rail ntd4302?1g ipak 369d (pb?free) 75 units / rail ntd4302t4g dpak 369c (pb?free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd4302 http://onsemi.com 6 package dimensions dpak (single gauge) case 369c issue e b d e b3 l3 l4 b2 m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.028 0.045 0.72 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 7. optional mold feature. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.114 ref 2.90 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw e bottom view z bottom view side view top view alternate construction note 7 style 2: pin 1. gate 2. drain 3. source 4. drain
ntd4302 http://onsemi.com 7 package dimensions 123 4 v s a k ?t? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? ipak case 369d issue c style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ntd4302/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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